1. Field of the invention
This invention relates to a DMA (Direct memory access) controller which has a function to temporarily release buses against external devices, under the condition in which the DMA controller holds a bus utility right obtained from a CPU.
2. Description of the prior art
A conventional DMA controller has a function to efficiently transfer a large amount of data at a high speed, without going by way of a CPU. In this instance, the DMA controller controls a direct data transfer between external devices, after having acquired a bus utility right from the CPU. In such a DMA controller, there are two kinds of transfer modes, one of which is a single transfer mode, and the other of which is a block (burst) transfer mode. The usage of buses in these transfer modes are different from each other.
In a single transfer mode, acquisition and relinquishment of a bus utility right between a CPU and a DMA controller is carried out at every data transfer. For example, the data transfer is carried out with the timing shown in FIG. 5.
The DMA controller, which is operated with the timing shown in FIG. 5, has a counter in which a transfer word number showing the amount of transfer data is stored. In the case where more than one of transfer words are stored in this counter and a transfer request signal (DREQ, not shown in the figure) is supplied from an external device into the DMA controller, the DMA controller sends a request signal for the bus utility right (HREQ) to the CPU to acquire the bus utility right. When the CPU accepts the request, it sends an enabling signal (HLDA) and temporarily gives the bus utility right to the DMA controller.
Once the DMA controller has acquired the bus utility right as mentioned above, it generates address information (A) and control signals for data (D) reading or writing (MR or MW), which are the similar ones as those generated from the CPU for a data transfer. Thus, the DMA controller executes one DMA transfer cycle.
Although the transfer request signal (DREQ) is in an active state, the DMA controller gives the bus utility right back to the CPU by withdrawing the bus utility request after one bus transfer cycle is completed. As a result, buses are released from the DMA controller, and so, the CPU and other external devices are allowed to use the buses again.
In that situation, however, the transfer for all the data to be transferred has not been completed yet. Therefore, the DMA controller should again send the request signal for the bus utility right to the CPU, and acquires the right to execute the second DMA transfer cycle.
As described above, in the single transfer mode, the DMA controller repeats the acquisition and relinquishment of the bus utility right against the CPU at every transfer cycle until the transfer word number counter becomes "0", and thus completing the data transfer.
The single transfer mode is used when one of the external devices, between which data are exchanged, has a lower access speed than those of the other devices. Buses are released at every one transfer cycle in this mode. Therefore, a particular external device cannot be allowed to occupy the buses for a long time. The buses are then available for a plurality of external devices, thus allowing distributive use of the buses.
On the other hand, in the single transfer mode, a certain period of time is needed to acquire and to relinquish the bus utility right at every one transfer cycle, besides the data transfer time. In other words, the overhead time for a data transfer becomes large in this mode, thus lowering the availability factor of the buses.
On the contrary, in a block transfer mode, once a DMA controller acquires a bus utility right to begin a DMA transfer cycle, the bus is occupied by the DMA controller until the transfer of all the data to be transferred is complete. In this case, the transfer word number counter becomes "0" to complete the data transfer.
This block transfer mode is utilized when the access speeds of two external devices, between which data are transferred, are high and data are transferred in a block unit. In this case, once a transfer cycle has begun, the buses are not allowed to be released until the data transfer is complete. A high availability factor is therefore obtained from this mode.
However, once a transfer begins, the DMA controller continues to occupy the buses. Therefore, to use the buses temporarily becomes difficult for other external devices. This fact causes a disadvantage for the distributive use of buses.
As explained above, in a prior art DMA controller, temporary release of buses is not allowed without taking steps to acquire and relinquish the bus utility right. This fact decreases the availability factor of buses, and causes difficulty for the distributive use of buses.